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DATA SHEET
MOS INTEGRATED CIRCUIT
PD3725A
5000-BIT x 3 CCD COLOR LINEAR IMAGE SENSOR
The PD3725A is a high sensitivity 5000-bit x 3 CCD (Charge Coupled Device) color linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3725A has 3 rows of 5000-bit photocell array and 6 rows of 2500-bit charge transferred register, so it is suitable for high resolution color image scanners and digital color copiers.
FEATURES
* Valid photocell * Line distance * Color filter * Resolution * Data rate * Power supply : 5000-bit x 3 : 112 m (8 lines) R(red) bit-G(green) bit, Gbit-B(blue)bit : Primary colors (red, green and blue), pigment filter (with light resistance 107lx*Hour) : 16 dot/mm across the shorter side of a B4-size (257 x 364 mm) sheet : 16 MHz MAX. : +12 V * Photocell's pitch : 14 m
* Drive clock level : CMOS output under 5 V operation * High speed scan : 320 s/line
CHANGED POINTS from the PD3725D-01 * Pins 18 and 15, 17 and 14, 11 and 8, 12 and 9 are each connected inside of the device (refer to BLOCK DIAGRAM). * The specification of the total transfer efficiency (TTE) is improved from 92 % to 93.5 % (MIN.) (refer to ELECTRICAL CHARACTERISTICS).
ORDERING INFORMATION
Part Number Package CCD linear image sensor 24-pin ceramic DIP (600 mil)
PD3725AD
The information in this document is subject to change without notice. Document No. S11324EJ1V0DS00 (1st edition) Date Published March 1996 P Printed in Japan
(c)
1996
PD3725A
BLOCK DIAGRAM
R1B
20
R2B
5
1A1
18
2A1
17
VOD 4 7 21 GND GND
VOUT2
22
CCD analog shift register 2 Transfer gate
16 ...........
TG1
S4999 S5000 D128
D127 S1 S2
(B)
...........
Photocell
VOUT1
23
Transfer gate CCD analog shift register 1
D133
D26
15 14
1A2 2A2 TG2
VOUT4
24
CCD analog shift register 4 Transfer gate
13 ...........
S4999 S5000 D128
D127 S1 S2
(G)
...........
Photocell
VOUT3
1
Transfer gate CCD analog shift register 3
D133
D26
12 11
2A3 1A3 TG3
VOUT6
2
CCD analog shift register 6 Transfer gate
10 ...........
S4999 S5000 D128
D127 S1 S2
(R)
...........
Photocell
VOUT5
3
Transfer gate CCD analog shift register 5
6
19
8
9
2L
1L
1A4
2A4
2
D133
D26
PD3725A
PIN CONFIGURATIONS (Top View) CCD linear image sensor 24-pin ceramic DIP (600 mil)
Signal output 3 (GREEN)
VOUT3
1
24
VOUT4 Signal output 4 (GREEN)
Signal output 6 (RED)
VOUT6
2
23
VOUT1 Signal output 1 (BLUE)
1
1
Signal output 5 (RED)
VOUT5
1
3
22
VOUT2 Signal output 2 (BLUE)
Output drain voltage
VOD
4
21
GND
Ground
Reset clock 2
R2B
5
20
R1B Reset clock 1
Last-stage shift register clock 2
2L
6
19
1L
Last-stage shift register clock 1
G
R
B
Ground
GND
7
18
1A1
Shift register clock 1
Shift register clock 1
1A4
8
17
2A1
Shift register clock 2
Shift register clock 2
2A4
9
16
TG1 Transfer gate clock 1
5000
5000
Shift register clock 1
1A3
5000
Transfer gate clock 3
TG3
10
15
1A2
Shift register clock 1
11
14
2A2
Shift register clock 2
Shift register clock 2
2A3
12
13
TG2 Transter gate clock 2
PHOTOCELL STRUCTURE DIAGRAM
12 m
2 m
14 m
Channel stopper
Aluminium electrode
3
PD3725A
ABSOLUTE MAXIMUM RATINGS (TA = +25 C)
Parameter Output drain voltage Shift register clock voltage Reset signal voltage Transfer gate signal voltage Operating ambient temperature Storage temperature VOD V1, V2 VR1B, VR2B VTG TA Tstg Symbol Ratings -0.3 to +15 -0.3 to +15 -0.3 to +15 -0.3 to +15 -25 to +60 -40 to +100 Unit V V V V C C
Caution Exposure to Absolute Maximum Rating for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 C)
Parameter Output drain voltage Shift register clock signal high level Shift register clock signal low level Reset signal high level Reset signal low level Transfer gate signal high level Transfer gate signal low level Data rate VOD V1H, V2H V1L, V2L VR1BH, VR2BH VR1BL, VR2BL VTGH VTGL 2 x fR1B, 2 x fR2B Symbol MIN. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3 - TYP. 12.0 5 0 5 0 5 0 2 MAX. 12.6 5.5 +0.5 5.5 +0.5 5.5 +0.5 16 Unit V V V V V V V MHz
Remark 1: 1A1 to 1A4, 1L
2: 2A1 to 2A4, 2L
4
PD3725A
ELECTRICAL CHARACTERISTICS
TA = +25 C, VOD = 12 V, foR1B, fR2B = 1 MHz, data rate = 2 MHz, storage time = 10 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 Vp-p
Parameter Saturation voltage
Symbol Vsat SER
Conditions
MIN. 1.0
TYP. 1.3 0.3 0.3 0.6
MAX. -
Unit V lx*s lx*s lx*s
Saturation exposure
SEG SEB
Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance
PRNU ADS DSNU PW ZO RR
VOUT = 500 mV Light shielding Light shielding -5
6 0.1 0.5 300 0.5 2.71 2.66 1.45 3.87 3.80 2.07 2 4 33 6 40 98
15 5 +5 500 1 5.03 4.91 2.70 5 8 47
% mV mV mW k V/lx*s V/lx*s V/lx*s % V ns %
Response
RG RB
Image lag Offset levelNote 1 Output fall delay timeNote 2 Total transfer efficiency Register imbalance Red response peak Green response peak Blue response peak Dynamic range Reset feed through noise
IL VOS td TTE RI
VOUT = 500 mV
fR1B, fR2B = 8 MHz, data rate = 16 MHz VOUT = 500 mV
93.5 0.0
4.0 630 540 460
% nm nm nm times
DR RFSN
Vsat/DSNU Light shielding
2600 300 500
mV
Notes 1. Refer to TIMING CHART 3, 5. 2. Each fall delay time of 1L and 2L (t11, t27 and t1, t37) is the TYP. value (refer to TIMING CHART 3, 5).
5
PD3725A
INPUT PIN CAPACITANCE
Parameter Symbol Pin name Pin No. 16 13 10 20 50 5 19 100 6 18 8 250 17 9 15 11 500 14 12 750 pF 380 pF 150 pF 80 pF 300 450 pF MIN. TYP. MAX. Unit
TG1
Transfer gate pin capacitance CTG
TG2 TG3 R1B
Reset clock pin capacitance
CR
R2B 1L
Last stage shift register clock pin capacitance
CL
2L 1A1 1A4
Shift register clock pin capacitance A
CA
2A1 2A4 1A2 1A3
Shift register clock pin capacitance B
CB
2A2 2A3
6
TIMING CHART 1
TG1, TG3 TG2 1A1 to 1A4, 1L 2A1 to 2A4, 2L
R1B R2B
G
R, B
0
1
2
3
13
60
61
62
63
64
65
66
D0 VOUT1, 3, 5
D2
D4
D8
D26
D122
D126
S1
S3
S5
D1 VOUT2, 4, 6
D3
D5
D25
D27
D123
D127
S2
S4
S6
Vacant transfer (26 bits)
Optical black (96 bits)
Invalid photocell (6 bits)
Valid photocell (5000 bits)
Caution Pins 18 (1A1) and 15 (1A2), 11 (1A3) and 8 (1A4) are each connected inside of the device, so do not input different timings to them. And also pins 17 (2A1) and 14 (2A2), 12 (2A3) and 9 (2A4) are each connected inside of the device, so do not input different timings to them (refer to BLOCK DIAGRAM).
PD3725A
7
8
TIMING CHART 2
TG1, TG3 TG2 1A1 to 1A4, 1L 2A1 to 2A4, 2L R1B
R2B
S4997 S4999 VOUT1, 3, 5 D128 D130 D132
S4996 S4998 S5000 D129 VOUT2, 4, 6
D131
D133
Invalid photocell (6 bits)
PD3725A
PD3725A
TIMING CHART 3 (Usual speed drive
t10
fR1B, fR2B = 1 to 5 MHz)
t1
1L, 1A1 to 1A4
t11 90%
10% t2
t6 t12 t16
2L, 2A1 to 2A4
t3
R2B
t4
t5
t13
R1B
t14
t15
td
VOUT2, 4, 6 VOS
90% 10% td
VOUT1, 3, 5 VOS
TIMING CHART 4
2L, 2A1 to 2A4
90% 10%
1L, 1A1 to 1A4
t7
t8
t9
t8
t7
TG2
t17 t18
t19
t18 t17
TG1, TG3
9
PD3725A
Recommended Timing
(Unit: ns) Symbol t1, t11 t2, t12 t3, t5, t13, t15 t4, t14 t6, t16 t7, t17 t8, t18 t9, t19 t10 MIN. 0 0 0 20 20 20 0 1000 100 TYP. 10 50 5 50 50 50 50 2000 500 MAX. - - - - - - - - -
1A, 2A cross points 1A, 2A cross points
1A
1L, 2A2A cross points 1L, cross points
2A
2 V or more
2 V or more
2 V or more
2A
1L
0.5 V or more
1A, 2L cross points 1A, 2L cross points
1A
2 V or more
2L
0.5 V or more
Remark 1. Adjust input resistance of each pin for cross points (1A, 2A), (1L, 2A) and (1A, 2L) 2. 1A: 1A1 to 1A4
2A: 2A1 to 2A4
10
PD3725A
TIMING CHART5 (High speed drive
t30 t21 90% t31
fR1B, fR2B = 5 to 8 MHz)
1A1 to 1A4
10%
2A1 to 2A4
t27
t26
1L
t37
t36
2L
t32 t33 t34 t35
R2B
t22 t23 t24 t25
R1B
td
90% VOUT2, 4, 6 VOS 10%
td
90% VOUT1, 3, 5 VOS 10%
11
PD3725A
Recommended Timing (High speed drive fR1B, fR2B = 5 to 8 MHz)
(Unit: ns) Symbol t21, t31 t22, t32 t23, t25, t33, t35 t24, t34 t26, t36 t27, t37 t30 MIN. 0 0 0 20 10 0 60 TYP. 10 30 5 t30/2 20 10 100 MAX. -- -- -- -- -- -- --
Caution
When driving PD3725A according to timing shown in TIMING CHART 3 at high speed, period of signal output is shorten, therefore data may not be sampled normally. To sample data normally, drive PD3725A according to timing shown in TIMING CHART 5. To extend the period of signal output, falling edge of last gate shift register clock 1L, 2L should be earlier than that of shift register clock 1A, 2A. When making the falling edge of 1L, 2L early, output signal is effected by noise from reset clock
R1B, R2B. To avoid the effection of this noise, the falling edge of R1B, R2B should be set
earlier. Driving at high speed, drive capability is necessary to be powered up. So design the peripheral circuit referring to peripheral circuit example 2.
12
PD3725A
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time(s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The peak/bottom ratio to the average output voltage of all the valid bits calculated by the following formula.
PRNU(%)=
VMAX. or VMIN. -1 n 1 Vj n j=1
x 100
n: Number of valid bits Vj: Output voltage of each bit
VMIN. Register Dark DC level VMAX.
1n n Vj j=1
S
4.
Average dark signal: ADS Output average voltage in light shielding n 1 Vj n j=1
ADS(mV) =
5.
Dark signal non-uniformity: DSNU The difference between peak or bottom output voltage in light shielding and ADS.
ADS Register Dark DC level DSNU MIN. DSNU MAX.
6.
Output impedance: ZO Output pin impedance viewed from outside.
7.
Response: R Output voltage divided by exposure (Ix*s). Note that the response varies with a light source.
13
PD3725A
8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light
ON
OFF
VOUT V1 VOUT IL = V1 VOUT x100 (%)
9.
Register Imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even bits, against the average output voltage of all the valid bits.
n 2
2 n RI =
(V2j
j=1
-1
- V2j) x 100 (%)
1 n
Vj
j=1
n
14
PD3725A
STANDARD CHARACTERISTIC CURVES (TA = +25 C)
DARK OUTPUT TEMPERATURE CHARACTERISTICS 8 2
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTICS
4 1
Relative Output Voltage
2
1
0.5
Relative Output Voltage
0.2 0.1 0 10 20 30 40 50 1 5 Storage Time (ms) 10 TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) B R G
0.25
0.1
Operating Ambient Temperature TA (C)
100
80
Response Ratio (%)
60
40
20
G B
0 400
500
600 Wavelength (nm)
700
800
15
R2B 2
TG1
16
PERIPHERAL CIRCUIT EXAMPLE 1
+12 V 0.1 F + _ 47 F/25 V
B1 B2 B3 10 + 47 F/25 V _ 47 47
1
VOUT3
VOUT4 VOUT1 VOUT2 GND
24 23 22 21
B4 B5 B6
2 VOUT6 3 4 VOUT5 VOD
5 R2B 6 2L 7 GND
R1B 20 1L 19 1A1 18 2A1 17 TG1 16 1A2
15
47 47
R1B 1
PD3725AD
8 1A4 9 2A4 10 10 TG3 11 1A3 12 2A3
B1 to B6 EQUIVALENT CIRCUIT +12 V 10 100 CCD VOUT 10 100 47 F/25 V + _
2A2 14 TG2
13
TG2
2 k
PD3725A
Remark Inverters: PD74HC04
PERIPHERAL CIRCUIT EXAMPLE 2 (For high speed drive)
+12 V 0.1 F + _ 47 F/25 V
B1 B2 B3 10 + 47 F/25 V _ 47 47
1
VOUT3
VOUT4 VOUT1 VOUT2 GND
24 23 22 21
B4 B5 B6
2 VOUT6 3 4 VOUT5 VOD
R2B 2
5 R2B
R1B 20
47 47
R1B 1
PD3725AD
6 2L 7 GND
1L 19 1A1 18 2A1 17 TG1 16 1A2
8 1A4 9 2A4
TG1
10
10
10 TG3 11 1A3 12 2A3
15
* *
10
TG2
* *
2A2 14 TG2
13
PD3725A
Remarks 1. Inverters: 74AC04
17
2. For
* inverter, use high speed inverter which has double driving capability of 74AC04
PD3725A
PACKAGE DIMENSIONS (Unit: mm)
CCD LINEAR IMAGE SENSOR 24PIN CERAMIC DIP (600 mil)
(Unit : mm) 2.62 2 Connecting part
14.4
11.00.6 20.030.6
1 Pin 1 index
90.01.3
85.01.2
0.460.05
1bit
3.51.0
2.54
1.270.05
3 Connecting part 0.970.3 3.30.35 4.33 NOTE 1 pin 1 index and 2 , 3 connecting parts are made of silver wax and plated with gold. As they are electrically connected with GND, be sure not to touch with other wirings on the board. 15.24
(2.33)
6.40.3 15.10.3
2.00.3
0.250.05
Name Glass cap
Dimensions 89.0 x 13.6 x 1.0
Refractive index 1.5
24D-1CCD-PKG-2
18
85.40.3
27.9
PD3725A
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Type of Through Hole Device
PD3725AD : CCD linear image sensor 24-pin ceramic DIP (600 mil)
Process Wave soldering (only to leads) Partial heating method Conditions Solder temperature: 260 C or below, Flow time: 10 seconds or less. Pin temperature: 260 C or below, Heat time: 10 seconds or less (Per each lead).
Caution For through hole devices, the wave soldering process must be applied only to leads, and make sure that the package body does not get jet soldered.
19
PD3725A
[MEMO]
20
PD3725A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
21
PD3725A
[MEMO]
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11

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